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8 mbit / 16 mbit single operation voltage serial flash memory with 100 mhz spi bus interface fea tures ? single power supply operation - low voltage range: 2.7 v - 3.6 v ? memory organization - PM25LV080B: 1m x 8 (8 mbit) - pm25lv016b: 2m x 8 (16 mbit) ? cost effective sector/block architecture - 8mb : uniform 4kbyte sectors / sixteen uniform 64kbyte blocks - 16mb : uniform 4kbyte sectors / thirty-two uniform 64kbyte blocks - bottom sector is configurable as one 4kbyte sector or four 1kbyte sectors ? serial peripheral interface (spi) compatible - supports spi modes 0 (0,0) and 3 (1,1) - maximum 33 mhz clock rate for normal read - maximum 100 mhz clock rate for fast read ? page program (up to 256 bytes) operation - typical 2 ms per page program ? sector, block or chip erase operation - typical 40 ms sector, block or chip erase ? software write protection - the block protect (bp2, bp1, bp0) bits allow partial or entire memory to be configured as read-only ? hardware write protection - protect and unprotect the device from write operation by write protect (wp#) pin ? low power consumption - typical 10 ma active read current - typical 15 ma program/erase current ? high product endurance - guarantee 100,000 program/erase cycles per single sector - minimum 20 years data retention ? industrial standard pin-out and package - 8-pin 208mil soic - 8-contact wson - optional lead-free (pb-free) package general description the PM25LV080B/016b are 8 mbit/16 mbit 3.0 volt-only serial peripheral interface (spi) flash memories. the devices are designed to support 33 mhz fastest clock rate in the industry in normal read mode, 100 mhz in fast read mode and the bottom 4 kbyte sector into four smaller 1 kbyte sectors features. the devices use a single low voltage, ranging from 2.7 volt to 3.6 volt, power supply to perform read, erase and program operations. the devices can be programmed in standard eprom programmers as well. the PM25LV080B/016b are accessed through a 4-wire spi interface consists of serial data input (sl), serial data output (so), serial clock (sck), and chip enable (ce#) pins. the devices support page program mode, 1 to 256 bytes data can be programmed into the memory in one program operation. these products are divided into uniform 4 kbyte sectors or uniform 64 kbyte blocks (sector group - consists of sixteen adjacent sectors). the devices have an innovative feature to configure the bottom 4 kbyte sector into four smaller 1 kbyte sectors for eliminating additional serial eeprom needed for storing data. this is a further cost reduction for overall system. the PM25LV080B/016b are manufactured on pflash?s advanced nonvolatile cmos technology. the devices are offered in 8-pin soic 208mil and 8-contact wson packages with operation frequency up to 100 mhz in fast read and 33 mhz in normal read mode. chingis technology corporation 1 issue date: octerber, 2006, rev: 0.1 PM25LV080B / 016b advanced information free datasheet http:///
2 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information pin descriptions symbol type description ce# input chip enable: ce# goes low activates the devices internal circuitries for device operation. ce# goes high deselects the devices and switches into standby mode to reduce the power consumption. when the devices are not selected, data will not be accepted via the serial input pin (sl), and the serial output pin (so) will remain in a high impedance state. sck input serial data clock s i inp ut s e ri al d ata inp ut so output serial data output gnd ground vcc device power supply wp# input write protect: a hardware program/erase protection for all or partial of memory array. when the wp# pin is pulled to low, whole or partial of memory array is write protected depends on the setting of bp2, bp1 and bp0 bits in the status register. when the wp# is pulled high, the devices are not write protected. hold# input hold: pause serial communication with the master device without resetting the serial sequence. connection diagrams 8-pin soic 5 6 7 8 1 2 3 4 vcc hold# sck si so gnd wp# ce# 5 6 7 8 1 2 3 4 vcc hold# sck si so gnd wp# ce# 8-contact wson free datasheet http:///
3 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information product ordering informa tion pm25lvxxx b -100 b c e temperature range c = commercial grade (-40c to +105c) package type b = 8-pin soic 208 mil (8b) q = 8-contact wson (8q) operating frequency -100 : 33mhz normal read and 100mhz fast read device number PM25LV080B/016b environmental attribute e = lead-free (pb-free) package blank = standard package part number operating frequency (mhz) package temperature range PM25LV080B-100bce pm25lv016b-100bce PM25LV080B-100qce pm25lv016b-100qce 100 8b 208mil soic commercial grade (-40 o c to +105 o c) 100 8q wson free datasheet http:///
4 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information block diagram hi g h volta g e generator control lo g ic i/o buffers and data latches address latch & counter 256 b y tes pa g e buffer status re g ister memor y arra y x-decoder y-decoder serial peripheral interface ce# wp# sck si so hold# free datasheet http:///
5 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information multiple PM25LV080B/016b devices can be serially con- nected onto the spi serial bus controlled by a spi mas- ter i.e. microcontroller as shown in figure 1. the devices support either of the two spi modes: mode 0 (0, 0) mode 3 (1, 1) spi modes description spi interface with (0, 0) or (1, 1) sdo sdi sck sck so si spi master (i.e. microcontroller) cs3 cs2 cs1 ce# wp# hold# hold# hold# spi memory device spi memory device spi memory device note: 1. the write protect (wp#) and hold (hold#) si g nals should be driven, hi g h or low as appropriate. sck so si sck so si ce# wp# ce# wp# figure 1. connection diagram among spi master and spi slaves (memory devices) the difference between these two modes is the clock polarity when the spi master is in stand-by mode: the serial clock remains at 0 (sck = 0) for mode 0 and the clock remains at 1 (sck = 1) for mode 1. please refer to figure 2. for both modes, the input data is latched on the rising edge of serial clock (sck), and the output data is available from the falling edge of sck. figure 2. spi modes supported sck sck si so mode 0 (0, 0) mode 3 (1, 1) msb msb free datasheet http:///
6 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information registers the PM25LV080B/016b are designed to interface directly with the synchronous serial peripheral interface (spi) of motorola mc68hcxx series of microcontrollers or all the spi interface equipped system controllers. the devices have two superset features can be enabled through the specific software instructions and configura- tion register: 1. configurable sector size: the memory array of PM25LV080B/160b are divided into uniform 4 kbyte sectors or uniform 64 kbyte blocks (sector group - consists of sixteen adjacent sectors). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x x sp0_3 sp0_2 sp0_1 sp0_0 scfg table 1. configuration register format table 2. configuration register bit definition bit name definition read/write bit 0 scfg sector configuration: "0" indicates the bottom sector is one 4 kbyte sector (default) "1" indicates the bottom sector is broken down to four 1 kbyte sectors this feature can be implemented only when bp0,bp1&bp2 of status register were enabled to "1" which is in protection mode. r/w bit 1 sp0_0 1 kbyte sector 0_0 protection: "0" indicates sector protection is disabled (default) "1" indicates sector protection is enabled r/w bit 2 sp0_1 1 kbyte sector 0_1protection: "0" indicates sector protection is disabled (default) "1" indicates sector protection is enabled r/w bit 3 sp0_2 1 kbyte sector 0_2 protection: "0" indicates sector protection is disabled (default) "1" indicates sector protection is enabled r/w bit 4 sp0_3 1 kbyte sector 0_3 protection: "0" indicates sector protection is disabled (default) "1" indicates sector protection is enabled r/w bit 5 - 6 res reserved for future (don't care) n/a bit 7 res reserved for future (don't use) n/a the devices have an option to configure the 4 kbyte bottom sector (sector 0) into four 1 kbyte smaller sectors (sector 0_0, sector 0_1, sector 0_2 and sector 0_3). the finer granularity sector size archi- tecture allows user to update data more efficiently. this feature allows user to eliminate the need of addtional serial eeprom. refer to table 1 for configuration register and table 2 for configuration register bit definition. free datasheet http:///
7 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information registers (continued) configuration register the configuration register is built by latchs need to be set each time after power-up before enabling the 1 kbyte smaller sector size and 1 kbyte sector write protection. the bit 0 - bit 7 of configuration register are set as 0s after power-up reset. therefore, the devices will be al- ways set as normal mode - the bottom sector set as 4 kbyte by default after power-up to maintain the back- ward-compatibility. the function of configuration register is described as following: scfg bit : the 1 kbyte smaller sector mode is enabled by writing 1 to scfg bit, then sector 0 is configured as sector 0_0, sector 0_1, sector 0_2 and sector 0_3. a sector erase (sector_er) instruction can be used to erase any one of those four 1 kbyte sectors. the scfg bit will be reset 0 state automatically at power on stage. thus, the 1 kbyte smaller sector mode is disabled at power on till scfg bit was set. the scfg bit only can be enabled to 1 when bp0, bp1&bp2 of status register were 1 state which in pro- tection mode. on the other word, scfg bit will be cleared to 0 state when bpx were 0 to disable the protection mode. sp0_x bits : the write protection to those four 1 kbyte sectors can be activated by writing 1s to the sp0_0, sp0_1, sp0_2 and sp0_3 bits. the 1 kbyte sector write protection function can only be enabled when the scfg is also enabled. the write configuration register (wrcr) instruction can be used to write 0s or 1s into configuration register. and the read configuration register (rdcr) instruc- tion can be used to read the setting of configuration register. refer to table 8 for instruction set. status register the status register contains wip and wel status bits to indicate the status of the devices, the block protec- tion bits (bp0, bp1 and bp2) to define the portion of memory blocks to be write protected, the bp0, bp1, bp2, and srwd are non-volatile memory cells that can be written by write status register (wrsr) instruction. the default value of bp0, bp1, bp2, and srwd bits were set as 0 at factory. once those bits are written as 0 or 1, it will not be changed by devices power-up or power-down until next wrsr instruction al- ters its value. the status register can be read by read status register (rdsr) instruction for its value and sta- tus. refer to table 8 for instruction set. the function of status register is described as following: wip bit : the write in progress (wip) bit can be used to detact the progress or completion of program or erase operation. when wip bit is 0, the devices are ready for write status register, program or erase operation. when wip bit is 1, the devices are busy. wel bit : the write enable latch (wel) bit indicates the status of internal write enable latch. when wel bit is 0, the write enable latch is disabled, all write opera- tions include write status register, write configuration reg- ister, page program, sector erase, block and chip erase operations are inhibited. when wel bit is 1, the write enable latch is enabled. then write operations are allowed. the wel bit is enabled by write enable (wren) instruc- tion. all write register, program and erase instructions must be preceded by a wren instruction every time. the wel bit can be disabled by write disable (wrdi) instruction or automatically return to reset state after the completion of a write instruction. bp2, bp1, bp0 bits : the block protection (bp2 , bp1, bp0) bits are used to define the portion of memory area to be protected. refer to table 5, 6 and 7 block write protection bits setting . when one of the combination of bp2, bp1 and bp0 bits were set as 1, the relevant memory area is protected. any program or erase opera- tion to that area will be prohibited. especially, the chip erase (chip_er) instruction is executed only if all the block protection bits are set as 0s. if scfg bit was enabled to support 1kb x4 sectores on sector 0, sector 0s protection status will respect sp0_x in configuration register and ignore bpx bits status whatever protection status. and srwd control bits to be set for status register write protection. refer to table 3 and table 4 for status reg- ister format and status register bit definition. free datasheet http:///
8 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information table 4. status register bit definition bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 srwd 0 0 bp2 bp1 bp0 wel wip table 3. status register format registers (continued) table 5. block write protect bits for PM25LV080B srwd bit : the status register write disable (srwd) bit is operated in conjuction with the write protection (wp#) signal to provide a hardware protection mode. when the srwd is set to 0, the status register is not write protected. when the srwd is set to 1 and the wp# is pulled low (v il ), the non-volatile bits of status register (srwd, bp2, bp1, bp0) become read-only and the wrsr instruction will be prohibited. if the srwd is set to 1 but wp# is pulled high (v ih ), the status register is still changeable by wrsr instruction. bit name definition read- /write non-volatile bit bit 0 wip write in progress bit: "0" indicates the device is ready "1" indicates the write cycle is in progress and the device is busy rno bit 1 wel write enable latch: "0" indicates the device is not write enabled (default) "1" indicates the device is write enabled r/w no bit 2 bp0 block protection bit: (see table 5 and table 6 for details) "0" indicates the specific blocks are not write protected (default) "1" indicates the specific blocks are write protected r/w yes bit 3 bp1 bit 4 bp2 bits 5 - 6 n/a reserved: always "0"s n/a bit 7 srwd status register write disable: (see table 7 for details) "0" indicates the status register is not write protected (default) "1" indicates the status register is write protected r/w yes status register bits protected memory area bp2 bp1 bp0 8 mbit 000 none 0 0 1 upper sixteenth (block : 15): 0f0000h - 0fffffh 0 1 0 upper ei g hth (two blocks :14 and 15): 0e0000h - 0fffffh 0 1 1 upper quarter (four blocks :12 to 15): 0c0000h - 0fffffh 1 0 0 upper half (ei g ht blocks :8 to 15): 080000h - 0fffffh 10 1 all blocks (sixteen blocks : 0 to 15): 000000h - 0fffffh 110 111 free datasheet http:///
9 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information registers (continued) table 7. block write protect bits for pm25lv016b status register bits protected memory area bp2 bp1 bp0 16 mbit 000 none 0 0 1 upper 32nd (block : 31): 1f0000h - 1fffffh 0 1 0 upper sixteenth (two blocks :30 and 31): 1e0000h - 1fffffh 0 1 1 upper eighth (four blocks :28 to 31): 1c0000h - 1fffffh 1 0 0 upper quarter (eight blocks :24 to 31): 180000h - 1fffffh 1 0 1 upper half (sixteen blocks :10 to 31): 100000h - 1fffffh 110 all blocks (32 blocks : 0 to 31): 000000h - 1fffffh 111 free datasheet http:///
10 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information protection mode the PM25LV080B/016b have two protection modes: hard- ware write protection and software write protection to prevent any irrelevant operation under a possible noisy environment and protect the data integrity. hardware write protection the devices provide two hardware write protection features: a. when input any program, erase or write status regis- ter instruction, the number of clock pulse will be checked whether it is a multiple of eight before the execution of such instruction. any incomplete instruc- tion command sequence will be ignored. b. the devices feature a write protection (wp#) pin to provide a hardware write protection method for bp2, bp1,bp0 abd srwd in the status register. (1)when the wp# is pulled low (v il ), the status register is write protected if the srwd bit is enabled (refer to table 7 for hardware write protection on status register). hence part or whole memory area can be write protected depends on the setting of bp2, bp1 and bp0 bits. (2) when the wp# is pulled high (v ih ), the status register is not protected, bp2,bp1,bp0 and srwd can be changed. software write protection the PM25LV080B/016b also provide two software write protection features: a. before the execution of any program, erase or write status register instruction, the write enable latch (wel) bit must be enabled by execution of the write enable (wren) instruction. if the wel bit is not en- abled first, the program, erase or write register in- struction will be ignored. b. the block protection (bp2, bp1, bp0) bits allow part or whole memory area to be write protected. table 8. hardware write protection on status register srwd wp# status register 0 low writable 1 low protected 0high writable 1high writable free datasheet http:///
11 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information the PM25LV080B/016b utilize an 8-bit instruction regis- ter. refer to table 8 instruction set for the detail instruc- tions and instruction codes. all instructions, addresses, and data are shifted in with the most significant bit (msb) first on serial data input (si). the input data on si is latched on the rising edge of serial clock (sck) after the chip enable (ce#) is driven low (v il ). instruction name instruction format hex code operation maximum frenquency wren 0000 0110 06h write enable 100 mhz wrdi 0000 0100 04h write disable 100 mhz rdsr 0000 0101 05h read status register 100 mhz wrsr 0000 0001 01h write status register 100 mhz read 0000 0011 03h read data bytes from memory at normal read mode 33 mhz fast_read 0000 1011 0bh read data bytes from memory at fast read mode 100 mhz rdid 1001 0000 90h read manufacturer and product id 100 mhz rdes 1010 1011 abh read electronic signature 100 mhz jedec id read 1001 1111 9fh read manufacturer and prduct id by jedec id command 100 mhz page_ prog 0000 0010 02h page program data bytes into memory 100 mhz rdcr 1010 0001 a1h read configuration register 100 mhz wrcr 1111 0001 f1h wri te confi guration register 100 mhz sector_er 1101 0111 0010 0000 d7h 20h sector erase, support both d7h and 20h command 100 mhz block_er 1101 1000 d8h block erase 100 mhz chip_er 1100 0111 0110 0000 c7h 60h chip erase 100 mhz table 9. instruction set device operation every instruction sequence starts with a one-byte in- struction code and might be followed by address bytes, data bytes, or address bytes and data bytes depends on the type of instruction. the ce# must be driven high (v ih ) after the last bit of the instruction sequence has been shifted in. hold operation the hold# is used in conjunction with the ce# to se- lect the PM25LV080B/016b. when the devices are se- lected and a serial sequence is underway, hold# can be used to pause the serial communication with the master device without resetting the serial sequence. to pause, the hold# must be brought low while the sck signal is low. to resume serial communi- cation, the hold# is brought high while the sck signal is low (sck may still toggle during hold). inputs to the sl will be ignored while the so is in the high impedance state. free datasheet http:///
12 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information 01 8 31 38 39 46 47 54 high impedance device id device id device id sck ce# si so instruction 9 7 1010 1011b 3 dummy bytes figure 3. read electronic signature sequence device operation (continued) p roduct identification d ata manufacturer id f irst b yte 9d h second byte 7fh device id: PM25LV080B 13h pm25lv016b 14h table 10. product identification read electronic signature operation the read electronic signature (rdes) instruction is for reading out the old style of 8-bit electronic signature, whose values are shown as table of id definitions. this is not same as rdid or jedec id instruction. its not recommended to use for new design. for new design , please use rdid or jedec id instruction. the rdes instruction code is followed by three dummy bytes, each bit being latched-in on si during the rising edge of sck. then the device id is shifted out on so with the msb first, each bit been shifted out during the falling edge of sck. the rdes instruction is ended by ce# goes high. the device id outputs repeatedly if con- tinuously send the additional clock cycles on sck while ce# is at low. free datasheet http:///
13 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information figure 4. read product identification sequence device operation (continued) read product identification operation the read product identification (rdid) instruction al- lows the user to read the manufacturer and product id of the devices. refer to table 10 product identification for pflash? manufacturer id and device id. the rdid in- struction code is followed by two dummy bytes and one byte address (a7~a0), each bit being latched-in on si during the rising edge of sck. if one byte address is initially set to a0 = 0, then the first manufacturer id (9dh) is shifted out on so with the msb first, the device id and the second manufacturer id (7fh), each bit been shifted out during the falling edge of sck. 0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 ... 15 14 13 3 2 1 0 2-byte dummy instruction = 0000 1011b high impedance ce# sck si so 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 1-byte address (1) 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 76543210 ce# sck si so 76543210 data out 2 data out 3 48 76543210 data out 1 49 50 51 52 53 54 55 if one byte address is initially set to a0 = 1, then device id will be read first, then followed by the first manufac- ture id (9dh) and then second manufacture id (7fh). the manufacture and device id can be read continuously, alternating from one to the others. the instruction is completed by driving ce# high. note : (1) address a0 = 0, will output the 1st manufacture id (9dh) first -> device id -> 2nd manufacture id (7fh) address a0 = 1, will output the device id -> 1st manufacture id (9d) -> 2nd manufacture id (7fh) free datasheet http:///
14 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information device operation (continued) read product identification by jedec id command the jedec id read instruction allows the user to read the manufacturer and product id of the devices. refer to table 9 product identification for pflash? manufac- turer id and device id. the second manufacturer id (7fh) is shifted out on so with the msb first after jedec id read command input, followed by the first manufac- turer id (9dh) and the device id, each bit been shifted out during the falling edge of sck. figure 5. read product identification by jedec id read sequence sck ce# si instruction 1001 1111b 0 8 15 23 24 31 7 16 high impedance so device id manufacture id1 manufacture id2 free datasheet http:///
15 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information device operation (continued) write enable operation the write enable (wren) instruction is used to set the write enable latch (wel) bit. the wel bit of the PM25LV080B/016b are set as write disable state after power-up. the wel bit must be write enabled before any write operation includes sector, block and write disable operation to protect the device against inadvertent writes, the write disable (wrdi) instruction resets the wel bit and dis- ables all write instructions. the wrdi instruction is not sck si so instruction = 0000 0110b hi-z ce# figure 6. write enable sequence figure 7. write disable sequence ce# sck si so instruction = 0000 0100b hi-z chip erase, page program, write status register, and write configuration register operations. the wel bit will be reset back to write disable state automatically after the completion of a write operation. the wren instruction is required before any above instruction is executed. required after the execution of a write instruction. the wel will be automatically reset. free datasheet http:///
16 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information device operation (continued) write status register operation the write status register (wrsr) instruction allows the user to enable or disable the block protection and status register write protection features by writting 0s 0 1 2 3 5 6 7 8 9 10 11 12 13 14 4 15 765 4 32 10 data in instruction = 0000 0001b high impedance ce# sck si so figure 9. write status register sequence or 1s into those non-volatile bp2, bp1, bp0 and srwd bits. the erase operation for those non-volatile bits are not required. read status register operation the read status register (rdsr) instruction provides access to the status register. during the execution of a program, erase or write status register operation, all other figure 8. read status register sequence ce# sck si 0 12 3 56 7 8 9 10 11 12 13 14 4 instruction = 0000 0101b so 765432 10 high impedance data out msb 15 instructions will be ignored except the rdsr instruction can be used for detecting the progress or completion of the operations by reading the wip bit of status register. free datasheet http:///
17 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information device operation (continued) 0 1 2 3 5 6 7 8 9 10 11 12 13 14 4 15 765 4 321 0 data in instruction = 1111 0001b high impedance ce# sck si so figure 11. write configuration register sequence the read configuration register (rdcr) instruction pro- vides access to the configuration register. this instruc- tion can be used to verify the configuration setting of figure 10. read configuration register sequence ce# sck si 0 12 3 56 7 8 9 10 11 12 13 14 4 instruction = 1010 0001b so 76543210 high impedance data out msb 15 bottom sector 0 and the write protection setting for each individual 1 kbyte sector (sector 0_0 ~ sector 0_3) within the sector 0. read configuration register operation write configuration register operation the write configuration register (wrcr) instruction al- lows user to enable or disable four smaller 1k byte sectors and protection for each 1k byte sector by writ- ing 0s or 1s into scfg and sp0_3 ~sp0_1 in the congiguration register. please refer table 2 for details. do not require wren command before this wrcr operation. because configuration register is a data latch architecture not a flash cell. free datasheet http:///
18 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information read data operation the read data (read) instruction is used to read memory data of PM25LV080B/016b under normal mode running up to 33 mhz. the read instruction is activated by pulling the ce# line of the selected device to low (v il ), and the read instruction code is transmitted via the sl line followed by three bytes address (a23 - a0) to be read. there are total 24 address bits will be shifted in, only the a ms (most- significant address) - a0 will be decoded and the rest of a23 - a ms can be dont cared. refer to table 10 for the related address key. upon completion, any data on the sl will be ignored. figure 12. read data sequence 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 32 33 34 36 35 37 38 ... 23 22 21 3 2 1 0 76543210 3-byte address instruction = 0000 0011b high impedance ce# sck si so 39 address PM25LV080B pm25lv016b a n a19 - a0 a20 - a0 don't care bits a23 - a20 a23 - a21 table 11. address key the first byte data d7 - d0 addressed (can be at any location) is then shifted out onto the so line. a single byte data or up to whole memory array can be read out in one read instruction. the address is automatically increamented to the next higher address after each byte of data is shifted out. the read operation can be termi- nated any time by driving the ce# high (v ih ) after the data comes out. when the highest address of the de- vices is reached, the address counter will roll over to the 000000h address allowing the entire memory to be read in one continuous read instruction. device operation (continued) free datasheet http:///
19 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information fast read data operation the PM25LV080B/016b also feature a fast read (fast_read) instruction. this fast_read instruction is used to read memory data in 100mhz clock rate where the fast_read instruction proceeding. the devices are first selected by driving ce# low (v il ). the fast_read instruction code followed by three bytes address (a23 - a0) and a dummy byte (8 clocks) is trasmitted via the si line, each bit being latched-in dur- ing the rising edge of sck. then the first data byte device operation (continued) figure 13. fast read data sequence 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 ... 23 22 21 3 2 1 0 3-byte address instruction = 0000 1011b high impedance ce# sck si so addressed is shifted out on so line, each bit being shifted out at a maximum frequency f ct , during the falling edge of sck. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address allowing the entire memory to be read with a single fast_read instruction. the fast_read instruction is terminated by driving ce# high (v ih ). 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 765 3 0 76543210 high impedance ce# sck si so 4 1 76543210 2 data out 1 data out 2 dummy byte 48 free datasheet http:///
20 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information device operation (continued) page program operation the page program (page_prog) instruction allow up to 256 bytes data to be programmed into memory in one program operation page by page. the destination of the memory to be programmed must be outside the pro- tected memory area set by the block protection (bp2, bp1, bp0) bits. a page_prog instruction attemps to program into a page which is write protected will be ignored. before the execution of page_prog instruction, the write enable latch (wel) must be en- abled through a write enable (wren) instruction. the page_prog instruction is activated, after the ce# is pulled low to select the device and staying low during the entire instruction sequence, by shifting in the page_prog instruction code, three address bytes and program data (1 to 256 bytes) to be programmed via the sl line. program operation will start immediately after the ce# is brought high, otherwise the page_prog instruction will not be executed. the internal control logic automatically handles the programming voltages and tim- ing. during a program operation, all instructions will be ignored except the rdsr instruction. the progress or completion of the program operation can be determined by reading the wip bit in status register through a rdsr instruction. if wip bit = 1, the program operation is still in progress. if wip bit = 0, the program operation has completed. a single page_prog instruction programs 1 to 256 consecutive bytes within a page if it is not write protected. if more than 256 bytes data are sent to the devices, the address counter will roll over on the same page and the previously latched data are discarded and the last 256 bytes data are kept to be programmed into the page. the starting byte can be anywhere within the same page. when the end of the page is reached, the address will wrap around to the beginning of the same page. if the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. a program operation can alter 1s into 0s, but an erase operation is required to change 0s back to 1s. the same byte cannot be reprogrammed without erasing the whole sector or block first. figure 14. page program sequence 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 32 33 34 2075 2076 2077 2078 2079 076 5 32 2 1 1430 23 22 21 1st byte data-in 256th byte data-in 3-byte address instruction = 0000 0010b high impedance ce# sck si so free datasheet http:///
21 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information erase operation the memory array of PM25LV080B/016b are organized into uniform 4 kbyte sectors or 64 kbyte uniform blocks (sector group - consists of sixteen adjacent sectors). the bottom sector (sector 0) of the devices can be con- figured into four 1 kbyte smaller sectors. before a byte can be reprogrammed, the sector or block which contains this byte must be erased first. in order to erase the devices, there are three erase instructions in- clude sector erase (sector_er), block erase (block_er) and chip erase (chip_er) instructions can be used. a sector erase operation allows to erase any individual sector without affecting the data in others. a block erase operation allows to erase any individual block. and a chip erase operation allows to erase the whole memory array of the devices. pre-programs the devices are not required prior to a sector erase, block erase or chip erase operation. sector erase operation a sector_er instruction erases a 4 kbyte sector or a 1 kbyte smaller sector (sector 0_3, sector 0_2, sector 0_1, sector 0_0) if the bottom sector 0 has been config- ured as four smaller sectors. before the execution of sector_er instruction, the write enable latch (wel) must be enabled through a write enable (wren) instruc- tion. the wel will be reset automatically after the completion of sector erase operation. the sector_er instruction is entered, after the ce# is pulled low to select the device and staying low during the entire instruction sequence, by shifting in the sector_er instruction code and three address bytes via the si. erase operation will start immediately after the ce# is pulled high, otherwise the sector_er in- struction will not be executed. the internal control logic automatically handles the erase voltage and timing. re- fer to figure 13 for sector erase sequence. during a erase operation, all instruction will be ignored except the read status register (rdsr) instruction. the progress or completion of the erase opertion can be determined by reading the wip bit in status register through a rdsr instruction. if wip bit = 1, the erase operation is still in progress. if wip bit = 0, the erase operation has been completed. device operation (continued) block erase operation a block erase (block_er) instruction erases a 64 kbyte block for the PM25LV080B/016b. before the execution of block_er instruction, the write enable latch (wel) must be enabled through a write enable (wren) instruc- tion. the wel will be reset automatically after the completion of block erase operation. the block_er instruction is entered, after the ce# is pulled low to select the device and staying low during the entire instruction sequence, by shifting in the block_er instruction code and three address bytes via the si. erase operation will start immediately after the ce# is pulled high, otherwise the block_er in- struction will not be executed. the internal control logic automatically handles the erase voltage and timing. re- fer to figure 14 for block erase sequence. chip erase operation a chip erase (chip_er) instruction erases the whole memory array of PM25LV080B/016b. before the execu- tion of chip_er instruction, the write enable latch (wel) must be enabled through a write enable (wren) instruction. the wel will be reset automatically after the completion of chip erase operation. the chip_er instruction is entered, after the ce# is pulled low to select the device and staying low during the entire instruction sequence, by shifting in the chip_er instruction code via the si. erase operation will start immediately after the ce# is pulled high, other- wise the chip_er instruction will not be executed. the internal control logic automatically handles the erase voltage and timing. refer to figure 15 for chip erase sequence. free datasheet http:///
22 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information figure 16. block erase sequence figure 17. chip erase sequence 01 234 567891011 28 29 30 31 0 1 2 3 21 22 23 ... 3-byte address instruction = 1101 1000b high impedance ce# sck si so 01234567 high impedance sck ce# si so instruction = 1100 0111b or 0110 0000b 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 0 1 2 3 21 22 23 ... 3-byte address instruction = 1101 0111b or 0010 0000b high impedance ce# sck si so figure 15. sector erase sequence device operation (continued) free datasheet http:///
23 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information block/sector address table 12. block/sector addresses of PM25LV080B/016b note: 1. sector 0 can be configured into four smaller 1 kbyte sectors (sector 0_0: 000000h - 0003ffh, sector 0_1: 000400h - 0007ffh, sector 0_2: 000800h - 000bffh, and sector 0_3: 000c00h - 000fffh). memory density block no. block size (kbytes) sector no. sector size (kbytes) address range 16 mbit block 0 64 sector 0 (1) 4 000000h - 000fffh sector 1 4 001000h - 001fffh :: : sector 15 4 00f000h - 00ffffh block 1 64 sector 16 4 010000h - 010fffh sector 17 4 011000h - 011fffh :: : sector 31 4 01f000h - 01ffffh block 2 64 020000h - 02ffffh ::: : : ::: : : block 13 64 0d0000h - 0dffffh block 14 64 0e0000h - 0effffh block 15 64 0f0000h - 0fffffh 8 mbit :: :: : :: : : : block 29 64 1d0000h - 1dffffh block 30 64 1e0000h - 1effffh block 31 64 1f0000h - 1fffffh : :: : : : : : : : : : : : : : : : : free datasheet http:///
24 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information dc and ac opera ting range absolute maximum ra tings (1) notes: 1. stresses under those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress rating only. the functional operation of the device or any other conditions under those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condition for extended periods may affected device reliability. 2. maximum dc voltage on input or i/o pins are v cc + 0.5 v. during voltage transitioning period, input or i/o pins may overshoot to v cc + 2.0 v for a period of time up to 20 ns. minimum dc voltage on input or i/o pins are -0.5 v. during voltage transitioning period, input or i/o pins may undershoot gnd to -2.0 v for a period of time up to 20 ns. temperature under bias -65 o c to +125 o c storage temperature -65 o c to +125 o c surface mount lead soldering temperature standard package 240 o c 3 seconds lead-free package 260 o c 3 seconds input voltage with respect to ground on all pins (2) -0.5 v to v cc + 0.5 v all output voltage with respect to ground -0.5 v to v cc + 0.5 v v cc (2) -0.5 v to +6.0 v part number PM25LV080B/016b operating temperature (commercial grade) -40 o c to 105 o c vcc power supply 2.7 v - 3.6 v free datasheet http:///
25 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information dc characteristics applicable over recommended operating range from: t ac = -40c to +105c, v cc = 2.7 v to 3.6 v (unless otherwise noted). symbol parameter min typ max units i cc1 vcc active read current 10 15 ma i cc2 vcc pro g ram/erase current 15 30 ma i sb1 vcc standby current cmos 50 m a i sb2 vcc standby current ttl 3 ma i li input leaka g e current 1 m a i lo output leaka g e current 1 m a v il input low volta g e-0.50.8v v ih input hi g h volta g e0.7v cc v cc + 0.3 v v ol output low volta g e i ol = 2.1 ma 0.45 v v oh output hi g h volta g e i oh = -100 m av cc - 0.2 v 2.7v < v cc < 3.6v v cc = 3.6v, ce# = v ih to v cc v in = 0v to v cc v in = 0v to v cc , t ac = 0 o c to 85 o c condition v cc = 3.6v at 33 mhz, so = open v cc = 3.6v at 33 mhz, so = open v cc = 3.6v, ce# = v cc free datasheet http:///
26 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information ac characteristics applicable over recommended operating range from t a = -40c to +105c, v cc = 2.7 v to 3.6 v c l = 1ttl gate and 10 pf (unless otherwise noted). symbol parameter min typ max units f ct clock frequency for fast read mode 0 100 mhz f c clock frequency for read mode 0 33 mhz t ri input rise time 8 ns t fi input fall time 8 ns t ckh sck high time 4 ns t ckl sck low time 4 ns t ceh ce# high time 25 ns t cs ce# setup time 10 ns t ch ce# hold time 10 ns t ds data in setup time 2 ns t dh data in hold time 2 ns t hs hold setup time 15 ns t hd hold time 15 ns t v output valid 8.5 ns t oh output hold time normal mode 0 ns t lz hold to output low z 200 ns t hz hold to output high z 200 ns t dis output disable time 100 ns t ec secter/block/chip erase time 40 100 ms t pp page program time 25 ms t w write status register time 40 100 ms t vcs v cc set-up time 50 m s free datasheet http:///
27 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information ac characteristics (continued) serial input/output timing (1) note: 1. for spi mode 0 (0,0) valid in ce# v il v ih sck v ih v ih v oh v il v il v ol si so t cs t ckh t ckl t ceh t dh t ds t v t dis t oh hi-z hi-z t ch free datasheet http:///
28 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information ac characteristics (continued) t hd t hd t hs t hs t hz t lz ce# sck hold# so hold timing typ max units conditions c in 46pf v in = 0 v c out 812pf v out = 0 v pin capacitance ( f = 1 mhz, t = 25c ) note: these parameters are characterized but not 100% tested. output test load input test waveforms and measurement level 3.3 v 1.8 k 1.3 k output pin 10 pf 0.8vcc 0.2vcc 1.5 v ac measurement level input note: 1. input pulse voltage : 0.2vcc to 0.8vcc. 2. input timing reference voltages : 0.3vcc to 0.7vcc. 3. output timing reference voltage : vcc/2. free datasheet http:///
29 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information power-up and power-down at power-up and power-down, the device must not be selected (ce# must follow the voltage applied on vcc) until vcc reaches the correct value: - vcc(min) at power-up, and then for a further delay of tvce - vss at power-down usually a simple pull-up resistor on ce# can be used to insure safe and proper power-up and power-down. to avoid data corruption and inadvertent write operations during power up, a power on reset (por) circuit is included. the logic inside the device is held reset while vcc is less than the por threshold value (vwi) during power up, the device does not respond to any instruction until a time delay of tpuw has elapsed after the moment that vcc rised above the vwi threshold. however, the correct operation of the device is not guaranteed if, by this time, vcc is still below vcc(min). no write status chip selection not allowed all write commands are rejected tvce read access allowed device fully accessible tpuw vcc vcc(max) vcc(min) reset state v (write inhibit) time power-up timing register, program or erase instructions should be sent until the later of: - tpuw after vcc passed the vwi threshold - tvce after vcc passed the vcc(min) level at power-up, the device is in the following state: - the device is in the standby mode - the write enable latch (wel) bit is reset at power-down, when vcc drops from the operating voltage, to below the vwi, all write operations are dis- abled and the device does not respond to any write instruction. symbol parameter min. max. unit t vce *1 vcc(min) to ce# low 10 us t puw *1 power-up time delay to write instruction 1 10 ms v wi *1 write inhibit voltage 2.1 2.3 v note : *1. these parameters are characterized only. free datasheet http:///
30 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information program/erase performance parameter unit typ max remarks sector erase time ms 40 100 from writing erase command to erase completion block erase time ms 40 100 from writing erase command to erase completion chip erase time ms 40 100 from writing erase command to erase completion page programming time ms 2 5 from writing program command to program completion parameter min typ unit test method endurance 100,000 cycles jedec standard a117 data retention 20 years jedec standard a103 esd - human body model 2,000 volts jedec standard a114 esd - machine model 200 volts jedec standard a115 latch-up 100 + i cc1 ma jedec standard 78 note: these parameters are characterized and are not 100% tested. note: these parameters are characterized and are not 100% tested. reliability characteristics free datasheet http:///
31 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information package type informa tion ` end view 5.38 5.18 top view side view 5.38 5.18 8.10 7.70 2.16 1.75 0.25 0.05 0.48 0.35 1.27 bsc 0.25 0.19 0.80 0.50 5.38 5.18 5.33 5.13 8b 8-pin jedec 208mil broad small outline integrated circuit (soic) package (measure in millimeters) free datasheet http:///
32 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information package type informa tion (continued) 8q 8-contact ulta-thin small outline no-lead (wson) package (measure in millimeters) 5.00 bsc top view side view 0.48 0.35 6.00 bsc 0.80 0.70 0.25 0.19 1.27 bsc bottom view pin 1 0.75 0.50 free datasheet http:///
33 chingis technology corporation issue date: octerber, 2006, rev: 0.1 PM25LV080B/016b advanced information revision hist or y date revision no. description of changes page no. july, 2006 0.0 advanced product specification all octerber, 2006 0.1 add power on/off sequence support 60h /20h as chip/sector erase command all free datasheet http:///

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